1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly to a driving circuit of a liquid crystal display device capable of variously adjusting a signal level in match with a characteristic of a liquid crystal panel by integrating a driver IC on the liquid crystal panel in order to make the liquid crystal panel in a compact size while reducing a manufacturing cost thereof.
2. Description of the Prior Art
In general, a CRT (cathode ray tube), which is one of display devices, is mainly used in monitors of televisions, various measurement apparatuses, and information terminals. However, the CRT has a heavy weight and a big size, so the CRT is not adaptable for electronic appliances having a small size and a light weight.
Accordingly, liquid crystal display devices having a slimmer and compact size with a light weight have been actively developed in order to substitute for CRTs. Recently, liquid crystal display devices have been developed as flat panel type display devices, and demand for the liquid crystal display devices has significantly increased.
Such a liquid crystal display is a sort of flat panel type display devices including two glass substrates and a liquid crystal layer formed between two glass substrates. Herein, gate lines and data lines defining pixel regions are formed on a lower substrate of the liquid crystal display panel such that gate lines and data lines are aligned in cross to each other. Also, a pixel electrode and a thin film transistor switched by a driving signal of the gate line in order to apply a signal of the data line to the pixel electrode, are aligned in each pixel region. In addition, a black matrix is aligned on an upper glass substrate of the liquid crystal display panel so as to prevent light from radiating into regions in which pixel electrodes are not formed. Also, a color filter layer is formed in each of the pixel regions by interposing the black matrix between pixel regions, and a common electrode is aligned at a front surface of the upper glass substrate.
FIG. 1 is a view showing a structure of a liquid crystal display device. Such liquid crystal display device mainly includes a liquid crystal panel 11 used for displaying images, in which a plurality of gate lines and data lines are aligned in cross to each other and thin film transistors are aligned at cross points of the gate lines and data lines, a source driver IC 13 for applying a driving voltage to the data lines of the liquid crystal panel 11, and a gate driver IC 15 for applying driving voltage to the gate lines of the liquid crystal panel 11.
In addition, even though it is not illustrated, the liquid crystal display device includes peripheral circuits, such as an LVDS unit and a timing controller, applying various control signals to the source driver IC 13 and the gate driver IC 15.
An operation of the gate driver IC 15 is shown as a timing view in FIG. 2.
That is, referring to FIG. 2, a CPV signal having a level of 3.3V, which is a clock signal, is inputted into the gate driver IC 15. Also, when an STV1 signal, which is a start pulse signal having a level identical to that of the CPV signal, is inputted into the gate driver IC 15. When the STV1 signal is maintained in a high level, an output pulse signal (out 1) of an out1 line is selected at a rising point of the CPV signal, so that the selected pulse signal (out 1) is shifted into a next line. Also, the shifted pulse signal is operated as a start pulse signal of the next line, so an output pulse signal (out 2) of an out2 line is selected at a rising point of the CPV signal.
In this manner, such as shown in FIG. 3, a gate output selected while the output pulse signal is being shifted to the next line is applied to a liquid crystal panel 11 through a shift register unit 15a, a level shift unit 15b, and a buffer 15c installed in a chip. At this time, a voltage applied to the liquid crystal panel 11 has a gate ON/OFF voltage level for driving a liquid crystal.
However, such a liquid crystal display device creates the voltage capable of driving a liquid crystal cell in an external circuit consisting of a single IC chip, so the degree of freedom for selecting designs of an external appearance of the liquid crystal display device may be limited.
Accordingly, in order to solve the above problem, a shift register shown in FIG. 4 and a level shifter shown in FIG. 5 have been proposed.
That is, the shift register shown in FIG. 4 includes n number of stages 121 to 12n sequentially connected to a start pulse input line and n number of level shifters 131 to 13n sequentially connected to output lines of the stages 121 to 12n for driving an m×n pixel array. The level shifters 131 to 13n and output lines 141 to 14n are connected to n number of row lines ROW1 to ROWn included in the pixel array, respectively.
The first stage 121 controlled by a start pulse SP and two clock signals selected from among four clock signals C1 to C4 outputs a clock signal to the next stage 122 and the first level shifter 131. Also, the first level shifter 131 receives one of four clock signals C1 to C4 outputted from the first stage 121, which is not inputted into the first stage 121. In addition, the first level shifter 131 is controlled by clock signals inputted thereto so as to select row lines ROWi connected to the pixel line.
Meanwhile, according to the level shifter as shown in FIG. 5, each of the stages 121 to 12n includes a first NMOS transistor T1 connected between a fourth node P4i of a previous stage 12i−1 and a first node P1 of a stage 12i, a second NMOS transistor T2 connected among the first node P1, a second node P2 and a basis voltage line 10, a third NMOS transistor T3 connected among a feeding line 8, a second clock signal line 6c and the second node P2, a fourth NMOS transistor T4 connected between the second node P2 and the basis voltage line 10, a first capacitor Cgd connected between a third node P3 and the basis voltage line 10, a fifth NMOS transistor T5 connected among the first node P1, a first clock signal line 6a and the third node P3, and a sixth NMOS transistor T6 connected among the second node P2, the third node P3 and the basis voltage line 10.
In addition, each of the level shifters includes a seventh NMOS transistor T7 connected among a second clock signal line 6b, a fifth node P5 and a sixth node P6, an eighth NMOS transistor T8 connected among the fifth node P5, a high voltage feeding line 11 and the sixth node P6, a second capacitor CLS connected between the sixth node P6 and an output line 14i, a ninth NMOS transistor T9 connected among the output line 14i, the high voltage feeding line 11 and a source electrode of the eighth NMOS transistor T8, and a tenth NMOS transistor T10 connected among the output line 14i, the basis voltage line 10 and a gate electrode of the seventh NMOS transistor T7.
However, if the level shifter having the above-mentioned construction is installed in the liquid crystal panel, it is difficult to deal with an internal gate line delay. In addition, it is difficult to precisely adjust a level if the level shifter is accommodated in the liquid crystal panel, thereby causing the shift register to malfunction.